1. Field of the Invention
The present invention pertains to digital logic circuits and, in particular, to a method and system for designing digital logic circuits containing functionally redundant transistor networks used to design ICs (integrated circuits).
2. Description of the Related Art
Integrated circuit technology represents the core of electronic engineering technology. Transistors form the basic components from which ICs are fabricated. Several basic techniques for placing and interconnecting transistors are known. The most popular and effective technologies are based on MOS (metal oxide semiconductor) technology. Several logic families have been developed for digital logic design based on underlying MOS fabrication technology, such as, for example, CMOS (complementary metal oxide semiconductor), NMOS, and PMOS. Each example logic family has advantages and disadvantages.
As a matter of contextual background, a brief review of existing logic families will be presented. The most popular logic family is based on CMOS technology. CMOS logic can be divided into static CMOS and dynamic CMOS logic families. Static CMOS is the most popularly used logic family.
Static logic circuitry is characterized by the fact that a global signal, namely a clock, is not used to synchronize the circuit. The output is solely a function of the input of the circuit, and is asynchronous with respect to the input. The timing of the circuit is defined exclusively by the static logic circuit's internal delay.
In dynamic logic, the output is synchronized by a global signal, viz. the clock. Thus, the output is a function of both the circuit's input(s) and the circuit's clock signal. That is, the timing of the circuit is defined both by the circuit's internal delay and the timing of the clock. Dynamic logic circuits typically operate faster than their static logic counterparts because their switching is based on dynamic charge storage.
Logic families, such as static CMOS, are comprised of both static and dynamic logic. Static CMOS is the type of logic most often referred to when static logic is discussed. Static CMOS is the most popular family of logic for the design of digital ICs. Static CMOS circuits typically have the same number of NMOS and PMOS transistors, wherein the n and p branches are duals of each other. An exemplary generic network structure of the static CMOS logic family is shown in FIG. 1.
It is noted that the generic network 100 includes a PMOS branch 5, a NMOS branch 10, inputs 15, an output 20, a ground connection 25, and a power connection 30. Static logic is fast, does not dissipate power in the steady state, and has good noise margin characteristics. It has a pull-up network which is implemented using, for example, PMOS transistors and a pull-down network which is implemented using NMOS transistors. Additional examples of static CMOS logic networks are shown in FIGS. 2 and 3.
FIG. 2 shows an exemplary CMOS circuit 200 for the function z=(abc)′, including PMOS branch 205 and NMOS branch 210. FIG. 3 illustrates a static CMOS circuit 300 for the function z=(a(b+c))′. Circuit 300 includes PMOS branch 305 and NMOS branch 310.
Pseudo-NMOS logic is cited herein for historical reasons. Pseudo-NMOS is not fast, it dissipates static power in a steady state (i.e., when the output is in the low state), and is sensitive to noise. It is an evolution of NMOS logic and is obtained by substituting an entire PMOS branch in a static logic implementation with a single PMOS transistor having its gate connected to ground so that the PMOS transistor is always conducting and leads the output node to the high state. If the ratio between the NMOS and PMOS transistor is well designed, the NMOS branch also conducts, thereby causing the output to discharge.
Dynamic logic families have a common characteristic, namely, the dynamic logic needs a pre-charge (or pre-discharge) transistor to lead some pre-charged nodes to a known state. The precharge (or pre-discharge) is accomplished during a pre-charge phase or memory phase of operation. During another phase of operation, the evaluation phase, the output has a stable value.
Some of the more popular and widely used dynamic logic families include Domino Logic, N-P Domino Logic/Zipper Logic, Clocked CMOS logic, NO RAce logic (NORA), and Pass-Transistor Logic (PTL). A generic domino logic network 400 is shown in FIG. 4. During the pre-charge phase of operation, the clock 405 is low so that the pre-charged node 410 before the static inverter 415 is high, and the output (Z) is low. During the evaluation phase, clock 405 is high so that the inputs of n-block 420 can discharge the pre-charged node 410 and lead the output (Z) to the high state. N-block 420 can be configured to perform any logical function. For example, an AOI (And-Or-Invert) gate 500 implemented using domino logic as shown in FIG. 5.
Several domino logic gates can be cascaded since each gate has its own output inverter, every gate can be driven with the same clock signal, and the evaluation phase lasts the time necessary for all of the gates to finish their input evaluation.
Moreover, domino logic has a limited area occupancy due to low number of PMOS transistors therein. However, it is not possible to implement inverting-structures and, as with all other dynamic logics, domino logic is subject to charge-sharing problems.
N-P domino logic, or zipper logic, as shown by a generic example thereof in FIG. 6, is an evolved version of domino logic. The logic blocks of this logic family alternate between NMOS and PMOS networks. The pre-charge and evaluate transistors are fed from the clock 635 and clockbar 40. It should be appreciated that the functions of the top and bottom transistors also alternate between pre-charge and evaluate.
This type of logic has a lower area occupancy since there is no need for a static inverter, however it also has a lower operating speed due to the presence of PMOS transistors.
Clocked CMOS logic is another dynamic logic family. A typical clocked CMOS gate is basically a three-state gate wherein when the clock is at a low state, the output is floating at the high impedance state. Clocked CMOS logic is principally used as a dynamic latch, as an interface between static logics and dynamic-pipelined logics.
NO RAce logic (NORA) is an evolution of N-P domino logic. The static inverter of domino logic is substituted with a clocked CMOS inverter. Since the output stage of every cell is also dynamic (i.e., a CMOS inverter), the NORA logic is more susceptible to charge-sharing problems than conventional domino logic
Pass-transistor logic (PTL) exploits the basic ability of a transistor to conditionally transmit information based on a condition at the gate, and the voltages at the drain and source terminals of the transistor can be brought to a similar level. In typical PTL designs, some transistors have neither their gate, source nor drain terminals connected to either the supply voltage or ground. Hence, PTL suffers from losses in signal strength and is typically not applied in environments where noise margins are critical.
A key problem with conventional logic families is that their properties critically depend on the topology of the underlying transistor network implementations defining the logic family. Differing topologies offer different design choices when implementing a transistor network. However, it is often desirable to have an implementation that provides the benefits of multiple topologies.
As an example, consider a static CMOS circuit wherein improved fall-time characteristics from multiple input pins to the output pin of the CMOS circuit is desired. With reference to circuit 200, let the target timing objective be to minimize the fall-time delay at node Z due to a transition at either node A or node B.
In general, the fall-time at Z caused by input transitions of transistors close to Z (as opposed to transistors closer to the ground node 225) is better than the fall-time at Z due to input transitions occurring at transistor inputs closer to the ground node 225. Note, this condition is not always guaranteed across all possible semiconductor fabrication processes and, other influencing sub-networks may be present. However, herein it is assumed that the transistors are all of the same type and size. Therefore, in the present example, the fall transition for the pin-pair A-Z is better than the fall transition for the pin-pair B-Z. If it is desired that the fall transition from B-Z be faster, the same network functionality (i.e., z=(abc)′) can be implemented with an alternative topology as shown in FIG. 7. However, if it is a design objective that both the A-Z and B-Z transitions be fast using the same IC logic topology, then conventional logic families do not offer a clear solution.
CMOS circuits are often designed with larger-sized PMOS gates where a balance is desired between rise time delays caused by PMOS transistors and fall time delays caused by NMOS transistors in order to account for the slower switching times of PMOS transistors, as compared to NMOS transistors. Some recent IC designs propose balancing the rise and fall times of simple NAND and NOR gates. Such suggested methods, however, rely on an ad hoc addition of transistors to arrive at balanced rise and fall times for the simple gates. Therefore, such proposed methods are clearly applicable only for simple gates, and there exists no systematic method or system for constructing or identifying such structures having balanced rise and fall times using simplified gates and/or more complex gates.